The Motivation: Why Open Silicon Matters
Every digital tool we rely on daily—our IDEs, compilers, browsers, and operating systems—eventually executes on proprietary black-box silicon. While the open-source software movement gave developers complete transparency and control over their software stacks, commercial desktop processor architectures have largely remained closed off.
Modern desktop-class computing shouldn't be a locked box. If an engineer wants to inspect, modify, optimize, or contribute to the hardware they execute code on, they should have that right.
"This philosophy is best demonstrated by XiangShan, an open-source, high-performance RISC-V processor led by the Institute of Computing Technology (CAS). Seeing an open-source architecture compete directly with modern commercial out-of-order cores proved that desktop-grade silicon does not have to belong exclusively to closed corporations."
Inspired by XiangShan's ambition and architecture, I started Zaqal: an open-source engineering project to design, implement, and verify a complete 64-bit Out-of-Order (OoO) superscalar RISC-V processor from the ground up using Chisel and Scala.
What is Zaqal?
Zaqal is a high-performance RISC-V core designed to bridge desktop-class microarchitecture with domain-specific AI acceleration. Instead of building a simple 5-stage educational processor, Zaqal tackles the real-world microarchitectural challenges required to run modern operating systems and demanding parallel workloads:
1. Decoupled Out-of-Order Pipeline
An 8-parcel fetch engine decoupled via a Fetch Target Queue (FTQ), multi-component branch prediction (FTB, TAGE, ITTAGE, SC, and RAS), 6-wide dynamic register renaming via a Physical Register File (PRF) and Rename Alias Table (RAT), distributed Issue Queues, and a 128-entry Reorder Buffer (ROB) ensuring precise architectural commits.
2. Privilege & System Compliance
Full hardware support for Machine (M-mode) and Supervisor (S-mode) privilege levels, complete CSR state handling, Clint timer, PLIC interrupt controller, and trap redirection capable of booting OpenSBI and handing execution over to an OS kernel like Linux.
3. Virtual Memory Subsystem
Sv39 hardware Page Table Walker (PTW) with multi-level TLB hierarchies (L1 ITLB/DTLB and shared L2 TLB) and hardware-accelerated virtual memory address translation for robust memory protection and multi-tasking environments.
4. Domain-Specific AI Acceleration (AMX & RVV 1.0)
Full compliance with the official RISC-V Vector Extension (RVV 1.0) featuring 128 physical vector registers (pv0–pv127), matching XiangShan Kunminghu parity, alongside custom 2D Matrix Units (AMX) with 8 Tile registers (tmm0–tmm7) designed specifically for hardware-accelerated INT8 and BF16 GEMM (General Matrix Multiply) operations.
5. Multi-Core Coherence
Scalable memory interconnect using the standard 5-channel TileLink-C protocol to handle Acquire/Grant memory operations and external Probe/Release directory-based cache snooping across private L1 caches, setting the stage for scalable multi-core compute clusters.
Zaqal Microarchitecture Specifications
The Development Methodology: AI-First Architecture & Rigorous Verification
Building an out-of-order processor as an independent engineer is historically a monumental undertaking. To make this feasible, Zaqal was planned and executed using an AI-first engineering workflow:
Before writing a single line of HDL, I structured a comprehensive 12-phase roadmap spanning processor bringup, MMU design, vector pipelines, matrix coprocessors, and multi-core interconnects.
I leveraged modern AI systems as collaborative thought partners—accelerating the generation of Chisel hardware modules, exploring corner-case trade-offs, and drafting interface bundles.
While AI accelerates drafting, digital silicon has zero tolerance for logic hallucinations. Every module—from ALU carry-breaking logic to TileLink arbitration—is manually verified through Verilator simulations and GTKWave.
Every single module—from the ALU carry-breaking logic and vector rename bypass paths to the trap commit boundary and TileLink channel arbitration—is manually verified, debugged, and validated through targeted testbenches, cycle-accurate Verilator simulations, and waveform inspection in GTKWave.
The Journey Ahead
Zaqal is an evolving engineering project. Having navigated through fundamental core bringup, privilege architectures, vector pipelines, and custom matrix engines, the focus is now on multi-core cache coherence and bus arbitration.
Open hardware is moving rapidly, and building Zaqal has reinforced that hands-on processor design is no longer confined to massive semiconductor giants.
Technical deep-dives into specific subsystems—including our AMX 2D tile engine and TileLink-C coherence state machines—will be published here as development continues.
Explore Zaqal on GitHub
Follow the progress, inspect the Chisel codebase, track the 12-phase roadmap, and review simulation testbenches directly in the public repository.
Architectural Inspiration (XiangShan)
Learn more about the open-source high-performance processor initiative led by the Institute of Computing Technology (CAS) that sparked Zaqal's architecture:
OpenXiangShan / XiangShan